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H83065 Datasheet(PDF) 159 Page - Renesas Technology Corp

Part # H83065
Description  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
PDF  963 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H83065 Datasheet(HTML) 159 Page - Renesas Technology Corp

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Section 6 Bus Controller
Rev. 4.00 Jan 26, 2006 page 137 of 938
REJ09B0276-0400
Bit 0—Refresh Pin Enable (RFSHE): Enables or disables
RFSH pin refresh signal output. If
areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1.
Bit 0
RFSHE
Description
0
RFSH pin refresh signal output disabled
(Initial value)
(
RFSH pin can be used as input/output port)
1
RFSH pin refresh signal output enabled
6.2.8
DRAM Control Register B (DRCRB)
—
TPC
RCW
RLW
0
Initial value
0
0
0
1
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
76543210
MXC1
MXC0
CSEL
RCYCE
Bit
DRCRB is an 8-bit readable/writable register that selects the number of address multiplex column
address bits for the DRAM interface, the column address strobe output pin, enabling or disabling
of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state
insertion between
RAS and CAS, and enabling or disabling of wait state insertion in refresh
cycles.
DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0.



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