H83065 datasheet(161/963 Pages) RENESAS

161 / 963 page

Section 6 Bus Controller

Rev. 4.00 Jan 26, 2006 page 139 of 938

REJ09B0276-0400

Bit 4—Refresh Cycle Enable (RCYCE): Enables or disables CAS-before-RAS refresh cycle

insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not

inserted regardless of the setting of this bit.

Bit 4

RCYCE

Description

Refresh cycles disabled

(Initial value)

DRAM refresh cycles enabled

Bit 3—Reserved: This bit cannot be modified and is always read as 1.

Bit 2—TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (TP) is to

be used for DRAM read/write cycles and CAS-before-RAS refresh cycles.

The setting of this bit does not affect the self-refresh function.

Bit 2

TPC

Description

1-state precharge cycle inserted

(Initial value)

2-state precharge cycle inserted

Bit 1—

RAS

RAS-CAS

CAS

CAS Wait (RCW): Controls wait state (Trw) insertion between T

r and Tc1 in DRAM

read/write cycles. The setting of this bit does not affect refresh cycles.

Bit 1

RCW

Description

Wait state (Trw) insertion disabled

(Initial value)

One wait state (Trw) inserted

Bit 0—Refresh Cycle Wait Control (RLW): Controls wait state (T

RW) insertion for CAS-before-

RAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles.

Bit 0

RLW

Description

Wait state (T

RW) insertion disabled

(Initial value)

One wait state (T

RW) inserted

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