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SH7014 Datasheet(PDF) 417 Page - Renesas Technology Corp

Part # SH7014
Description  32-Bit RISC Microcomputer
PDF  754 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7014 Datasheet(HTML) 417 Page - Renesas Technology Corp

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13. High Speed A/D Converter
⎯ SH7014 ⎯
Rev.5.00 Sep. 27, 2007 Page 383 of 716
REJ09B0398-0500
13.4.5
Buffer Operation
When conversion ends on the relevant channel, the conversion result is stored in the ADDR, and
simultaneously, the previously stored result is transferred to another ADDR. Buffer operation can
be selected from the following:
• AN0 → ADDRA → ADDRB (Two-stage, one-group operation)
• AN0 → ADDRA → ADDRC, AN1 → ADDRB → ADDRD (Two-stage, two-group
operation)
• AN0 → ADDRA → ADDRB → ADDRC → ADDRD (Four-stage, one-group operation)
To use in combination with simultaneous sampling, set GRP = 1, BUFE1, BUFE0 = B'10 and
CH2 = 0. Buffer operation timing is shown in figure 13.7.



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