SH7014 datasheet(536/754 Pages) RENESAS

536 / 754 page

18. 128 kB Flash Memory (F-ZTAT)

Rev.5.00 Sep. 27, 2007 Page 502 of 716

REJ09B0398-0500

18.5.3

Erase Block Register 1 (EBR1)

EBR1 is an 8-bit readable/writable register that specifies the flash memory erase area block by

block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby

mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin

and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block

can be erased. Other blocks are erase-protected. Set only one bit in EBR1 (more than one bit

cannot be set). When on-chip flash memory is disabled, a read will return H'00, and writes are

invalid.

The flash memory block configuration is shown in table 18.4.

Bit:

EB7

EB6

EB5

EB4

EB3

EB2

EB1

EB0

Initial value:

R/W:

R/W

Table 18.4

Flash Memory Erase Blocks

Block (Size)

Address

EB0 (32 kB)

H'000000 to H'007FFF

EB1 (32 kB)

H'008000 to H'00FFFF

EB2 (32 kB)

H'010000 to H'017FFF

EB3 (28 kB)

H'018000 to H'01EFFF

EB4 (1 kB)

H'01F000 to H'01F3FF

EB5 (1 kB)

H'01F400 to H'01F7FF

EB6 (1 kB)

H'01F800 to H'01FBFF

EB7 (1 kB)

H'01FC00 to H'01FFFF

SH7014 Datasheet(PDF) 536 Page - Renesas Technology Corp

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