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SH7713 Datasheet(PDF) 373 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 373 Page - Renesas Technology Corp |
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373 / 904 page ![]() Section 12 Bus State Controller (BSC) Rev.1.50 Aug. 30, 2006 Page 333 of 860 REJ09B0288-0150 CMNCR CS0WCR CS6BWCR CS0BCR CS6BBCR SDCR RTCSR RTCNT RTCOR Comparator Bus mastership controller Wait controller Area controller Internal master module Internal slave module Memory controller Refresh controller Interrupt controller [Legend] BSC CS0, CS2, CS3, CS4, CS5A, CS5B, CS6A, CS6B WAIT MD5 to MD3 IOIS16 A25 to A0, D31 to D0 REFOUT BACK BREQ BS, RD/WR, RD, WE3(BE3) to WE0(BE0), RAS, CAS, CKE, DQMxx, CE2A, CE2B CMNCR: CSnWCR: CSnBCR: SDCR: RTCSR: RTCNT: RTCOR: Common control register CSn space wait control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) CSn space bus control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) SDRAM control register Refresh timer control/status register Refresh timer counter Refresh time constant register Figure 12.1 Block Diagram of BSC |
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