SH7713 datasheet(376/904 Pages) RENESAS

376 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 336 of 860

REJ09B0288-0150

12.3

Area Overview

12.3.1

Area Division

In the architecture of this LSI, both logical spaces and physical spaces have 32-bit address spaces.

The upper three bits divide into the P0 to P4 areas, and specify the cache access method. For

details see section 6, Cache. The remaining 29 bits are used for division of the space into ten areas

(address map 1) or eight areas (address map 2) according to the MAP bit in CMNCR setting. The

BSC performs control for this 29-bit space.

As listed in tables 12.2 and 12.3, this LSI can be connected directly to eight areas of memory, and

it outputs chip select signals (

CS0, CS2 to CS4, CS5A, CS5B, CS6A, and CS6B) for each of them.

CS0 is asserted during area 0 access; CS5A is asserted during area 5A access when address map 1

is selected; and

CS5B is asserted when address map 2 is selected.

12.3.2

Shadow Area

Areas 0, 2 to 4, 5A, 5B, 6A, and 6B are decoded by physical addresses A28 to A25, which

correspond to areas 000 to 111. Address bits 31 to 29 are ignored. This means that the range of

area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space

is the address space in P1 to P3 areas obtained by adding to it H'20000000

× n (n = 1 to 6).

The address range for area 7 is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 +

H'20000000

× n to H'1FFFFFFF + H'20000000 × n (n = 0 to 6) corresponding to the area 7

shadow space is reserved, so do not use it.

Area P4 (H'E0000000 to H'EFFFFFFF) is an I/O area and is assigned for internal register

addresses. Therefore, area P4 does not become shadow space.

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