SH7713 datasheet(374/904 Pages) RENESAS

374 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 334 of 860

REJ09B0288-0150

12.2

Input/Output Pins

The configuration of pins in this module is shown in table 12.1.

Table 12.1

Pin Configuration

Name

I/O

Function

A25 to A0

Address bus

D31 to D0

I/O

Data bus

Bus cycle start

Asserted when a normal space, burst ROM (clock

synchronous/asynchronous), or PCMCIA is accessed. Asserted by the

same timing as

CAS in SDRAM access.

CS0, CS2 to CS4

Chip select

CS5A

Chip select

Active only for address map 1

CS5B/CE1A

Chip select

Corresponds to PCMCIA card select signals D7 to D0 when the

PCMCIA is used.

CE2A

Corresponds to PCMCIA card select signals D15 to D8 when the

PCMCIA is used.

CS6A

Chip select

Active only for address map 1

CS6B/CE1B

Chip select

Corresponds to PCMCIA card select signals D7 to D0 when the

PCMCIA is used.

CE2B

Corresponds to PCMCIA card select signals D15 to D8 when the

PCMCIA is used.

RD/

Read/write

Connects to

WE pins when SDRAM or byte-selection SRAM is

connected.

Read pulse signal (read data output enable signal)

A strobe signal to indicate the memory read cycle when the PCMCIA is

used.

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