SH7713 datasheet(379/904 Pages) RENESAS

379 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 339 of 860

REJ09B0288-0150

Table 12.3

Address Space Map 2 (CMNCR.MAP = 1)

Physical Address

Area

Memory to be Connected

Capacity

′00000000 to H′03FFFFFF

Area 0

Normal memory*

Burst ROM (Asynchronous)

Burst ROM (Synchronous)

64 Mbytes

′04000000 to H′07FFFFFF

Area 1

Internal I/O register area*

64 Mbytes

′08000000 to H′0BFFFFFF

Area 2

Normal memory*

Byte-selection SRAM

SDRAM

64 Mbytes

′0C000000 to H′0FFFFFFF

Area 3

Normal memory*

Byte-selection SRAM

SDRAM

64 Mbytes

′10000000 to H′13FFFFFF

Area 4

Normal memory*

Byte-selection SRAM

Burst ROM (Asynchronous)

64 Mbytes

′14000000 to H′17FFFFFF

Area 5*

Normal memory*

Byte-selection SRAM

PCMCIA

64 Mbytes

′18000000 to H′1BFFFFFF

Area 6*

Normal memory*

Byte-selection SRAM

PCMCIA

64 Mbytes

′1C000000 to H′1FFFFFFF

Area 7

Reserved area*

64 Mbytes

Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct

operation cannot be guaranteed.

2. For area 5, CS5BBCR and CS5BWCR are valid.

For area 6, CS6BBCR and CS6BWCR are valid.

3. Set the top three bits of the address to 101 to allocate in the P2 space.

4. Memory that has an interface such as SRAM.

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