SH7713 datasheet(509/904 Pages) RENESAS

509 / 904 page

Section 13 Direct Memory Access Controller (DMAC)

Rev.1.50 Aug. 30, 2006 Page 469 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Descriptions

R/W

DMA Enable

Enables or disables the DMA transfer. In auto-request

mode, DMA transfer starts by setting the DE bit and DME bit

in DMAOR to 1. In this time, all of the bits TE, NMIF in

DMAOR, and AE in DMAOR must be 0. In an external

request or peripheral module request, DMA transfer starts if

DMA transfer request is generated by the devices or

peripheral modules after setting the bits DE and DME to 1.

In this case, however, all of the bits TE, NMIF, and AE must

be 0 as in the case of auto-request mode. Clearing the DE

bit to 0 can terminate the DMA transfer.

0: DMA transfer disabled

1: DMA transfer enabled

Note:

Only 0 can be written to clear the flag.

13.3.5

DMA Operation Register (DMAOR)

DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the

DMA transfer. This register indicates the DMA transfer status.

DMAOR is initialized to H

′0000 at a reset and retains the current value in standby or module

standby mode.

Bit

Bit Name

Initial

Value

R/W

Description

15 to



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

PR1

PR0

R/W

Priority Mode

Select the priority level between channels when there are

transfer requests for multiple channels simultaneously.

00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5

01: Fixed mode 2: CH0 > CH2 > CH3 > CH1 > CH4 > CH5

10: Reserved (setting prohibited)

11: All channel round-robin mode

SH7713 Datasheet(PDF) 509 Page - Renesas Technology Corp

SH7713 Datasheet(HTML) 509 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL