SH7713 datasheet(505/904 Pages) RENESAS

505 / 904 page

Section 13 Direct Memory Access Controller (DMAC)

Rev.1.50 Aug. 30, 2006 Page 465 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

R/W

Transfer End Level

Specifies the TEND signal output is high active or low

active.

This bit is valid only in CHCR0 and CHCR1.This bit is

reserved and always read as 0 in CHCR2 to CHCR5. The

write value should always be 0.

0: Low-active output of TEND

1: High-active output of TEND

21 to



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R/W

Acknowledge Mode

Specifies whether the DACK is output in data read cycle or

in data write cycle in dual address mode.

In single address mode, the DACK is always output

regardless of the specification by this bit.

This bit is valid only in CHCR0 and CHCR1.This bit is

reserved and always read as 0 in CHCR2 to CHCR5. The

write value should always be 0.

0: DACK output in read cycle (Dual address mode)

1: DACK output in write cycle (Dual address mode)

R/W

Acknowledge Level

Specifies the DACK signal output is high active or low

active.

This bit is valid only in CHCR0 and CHCR1.This bit is

reserved and always read as 0 in CHCR2 to CHCR5. The

write value should always be 0.

0: Low-active output of DACK

1: High-active output of DACK

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