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SH7713 Datasheet(PDF) 507 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 507 Page - Renesas Technology Corp

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Section 13 Direct Memory Access Controller (DMAC)
Rev.1.50 Aug. 30, 2006 Page 467 of 860
REJ09B0288-0150
Bit
Bit Name
Initial
Value
R/W
Description
11
10
9
8
RS3
RS2
RS1
RS0
0
0
0
0
R/W
R/W
R/W
R/W
Resource Select
Specify which transfer requests will be sent to the DMAC.
The change of transfer request source should be done in the
state that the DMA enable bit (DE) is cleared to 0.
0000: External request, dual address mode
0010: External request, single address mode
External address space
→ external device with DACK
0011: External request, single address mode
External device with DACK
→ external address space
0100: Auto request
1000: DMA extension resource selector
Other than above: Reserved (setting prohibited)
Note: An external request specification is valid only in
CHCR0 and CHCR1. None of the external request
specification can be selected in CHCR2 to CHCR5.
7
6
DL
DS
0
0
R/W
R/W
DREQ Level and DREQ Edge Select
Specify the sampling method of the DREQ pin input and the
sampling level.
These bits are valid only in CHCR0 and CHCR1. These bits
are reserved and always read as 0 in CHCR2 to CHCR5.
The write value should always be 0.
In channels 0 and 1, also, if the transfer request source is
specified as an on-chip peripheral module or if an auto-
request is specified, the specification by this bit is invalid.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
5
TB
0
R/W
Transfer Bus Mode
Specifies the bus mode when the DMA transfers data.
0: Cycle steal mode
1: Burst mode



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