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SH7713 Datasheet(PDF) 543 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 543 Page - Renesas Technology Corp

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Section 14 Timer Unit (TMU)
Rev.1.50 Aug. 30, 2006 Page 503 of 860
REJ09B0288-0150
14.4
Interrupts
The interrupt source of TMU is underflow interrupt (TUNI).
14.4.1
Status Flag Set Timing
The UNF bit is set to 1 when the TCNT underflows. Figure 14.5 shows the timing.
P
φ
TCNT
Underflow
signal
UNF
TUNI
TCOR value
H'00000000
Figure 14.5 UNF Set Timing
14.4.2
Status Flag Clear Timing
The status flag can be cleared by writing 0 from the CPU. Figure 14.6 shows the timing.
P
φ
Peripheral address bus
UNF
TCR address
T1
T2
TCR write cycle
T3
Figure 14.6 Status Flag Clear Timing



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