SH7713 datasheet(539/904 Pages) RENESAS

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Section 14 Timer Unit (TMU)

Rev.1.50 Aug. 30, 2006 Page 499 of 860

REJ09B0288-0150

Bit

Bit Name

Initial Value R/W

Description

UNIE

R/W

Underflow Interrupt Control

Controls enabling of interrupt generation when the

status flag (UNF) indicating TCNT underflow has been

set to 1.

0: Interrupt due to UNF (TUNI) is disabled

1: Interrupt due to UNF (TUNI) is enabled

4, 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

TPSC2

TPSC1

TPSC0

R/W

Timer Prescaler 2 to 0

Select the TCNT count clock.

000: Count on P

φ/4

001: Count on P

φ/16

010: Count on P

φ/64

011: Count on P

φ/256

100: Reserved (Setting prohibited)

101: Reserved (Setting prohibited)

110: Reserved (Setting prohibited)

111: Reserved (Setting prohibited)

14.2.3

Timer Constant Registers (TCOR)

The TMU has three timer constant registers (TCOR), one for each channel. The TCOR registers

set the value to be set in TCNT when TCNT underflows.

The TCOR registers are 32-bit readable/writable registers. They are initialized to H'FFFFFFFF by

a power-on reset or manual reset, but are not initialized, and retain their contents, in standby

mode.

14.2.4

Timer Counters (TCNT)

The TMU has three timer counters (TCNT), one for each channel. The timer counters (TCNT)

counts down upon input of a clock. The input clock is selected using the TPSC2 to TPSC0 bits in

the timer control registers (TCR).

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