SH7713 datasheet(538/904 Pages) RENESAS

538 / 904 page

Section 14 Timer Unit (TMU)

Rev.1.50 Aug. 30, 2006 Page 498 of 860

REJ09B0288-0150

Bit

Bit Name

Initial Value

R/W

Description

STR0

R/W

Counter Start 0

Selects whether to run or halt TCNT0.

0: TCNT0 count halted

1: TCNT0 counts

14.2.2

Timer Control Registers (TCR)

The timer control registers (TCR) control the timer counters (TCNT) and interrupts. The TMU has

three TCR registers, one for each channel.

The TCR registers control the issuance of interrupts when the flag indicating timer counters

(TCNT) underflow has been set to 1, and also carry out counter clock selection.

The TCR registers are 16-bit readable/writable registers. They are initialized to H'0000 by a

power-on reset and manual reset, but are not initialized, and retain their contents, in standby mode.

Bit

Bit Name

Initial Value R/W

Description

15 or 9



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

UNF

R/W

Underflow Flag

Status flag that indicates occurrence of a TCNT

underflow.

0: TCNT has not underflowed

[Clearing condition]

0 is written to UNF

1: TCNT has underflowed

[Setting condition]

TCNT underflows*

Note: * Contents do not change when 1 is written to

UNF.

7, 6



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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