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SH7713 Datasheet(PDF) 535 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 535 Page - Renesas Technology Corp |
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535 / 904 page  Section 14 Timer Unit (TMU) Rev.1.50 Aug. 30, 2006 Page 495 of 860 REJ09B0288-0150 Section 14 Timer Unit (TMU) This LSI includes a three-channel (channel 0 to 2) 32-bit timer unit (TMU). 14.1 Features The TMU has the following features: • Each channel is provided with an auto-reload 32-bit down counter • All channels are provided with 32-bit constant registers and 32-bit down counters for an auto- reload function that can be read or written to at any time • All channels generate interrupt requests when the 32-bit down counter underflows (H'00000000 → H'FFFFFFFF) • Allows selection among 4 counter input clocks: Pφ/4, Pφ/16, Pφ/64, and Pφ/256 Note: P φ is the internal clock for peripheral modules. See section 11, On-Chip Oscillation Circuits, for more information on the clock pulse generator. 14.1.1 Block Diagram Figure 14.1 shows a block diagram of the TMU. |
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