 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SH7713 Datasheet(PDF) 531 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7713 Datasheet(HTML) 531 Page - Renesas Technology Corp |
|
|
531 / 904 page  Section 13 Direct Memory Access Controller (DMAC) Rev.1.50 Aug. 30, 2006 Page 491 of 860 REJ09B0288-0150 CKIO DREQ (Rising edge) DACK (High active) CPU CPU DMAC DMAC Bus cycle Non sensitive period Burst acceptance Figure 13.14 Example of DREQ Input Detection in Burst Mode Edge Detection CKIO CPU CPU DMAC CKIO CPU CPU DMAC DMAC 1st acceptance 1st acceptance Acceptance start Acceptance start Acceptance start Bus cycle DREQ (Overrun 0 at high level) DACK (Active-high) Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) Non sensitive period Non sensitive period 2nd acceptance 2nd acceptance 3rd acceptance Figure 13.15 Example of DREQ Input Detection in Burst Mode Level Detection CKIO DACK (High active) DREQ TEND (High active) Bus cycle End of DMA transfer DMAC CPU CPU CPU DMAC Figure 13.16 Example of DMA Transfer End Timing (Cycle Steal Level Detection) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
