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SH7713 Datasheet(PDF) 548 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 548 Page - Renesas Technology Corp |
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548 / 904 page ![]() Section 15 Realtime Clock (RTC) Rev.1.50 Aug. 30, 2006 Page 508 of 860 REJ09B0288-0150 • RTC control register 1 (RCR1) • RTC control register 2 (RCR2) • RTC control register 3 (RCR3) 15.3.1 64-Hz Counter (R64CNT) R64CNT indicates the state of the divider circuit (RTC prescaler and R64CNT) between 64 Hz and 1 Hz. R64CNT is reset to H'00 by setting the RESET bit in RCR2 or the ADJ bit in RCR2 to 1. R64CNT is an 8-bit read-only register and not initialized by a power-on reset or manual reset, or in standby mode. Bit Bit Name Initial Value R/W Description 7 0 R Reserved This bit is always read as 0. 6 to 0 R 64-Hz Counter Each bit (bits 6 to 0) indicates the state of the RTC divider circuit between 64 and 1Hz. Bit Frequency 6: 1 Hz 5: 2 Hz 4: 4 Hz 3: 8 Hz 2: 16 Hz 1: 32 Hz 0: 64 Hz 15.3.2 Second Counter (RSECCNT) RSECCNT is used for setting/counting in the BCD-coded second section. The count operation is performed by a carry for each second of the 64-Hz counter. The range of second can be set is 0 to 59 (decimal). Errant operation will result if any other value is set. Carry out write processing after stopping the count operation with the START bit in RCR2. |
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