SH7713 datasheet(783/904 Pages) RENESAS

783 / 904 page

Section 22 User Debugging Interface (H-UDI)

Rev.1.50 Aug. 30, 2006 Page 743 of 860

REJ09B0288-0150

22.4.2

Reset Configuration

Table 22.4

Reset Configuration

ASEMD0*1

RESETP

TRST

Chip State

Normal reset and H-UDI reset*

Normal reset*

H-UDI reset only

Normal operation

Reset hold*

In ASE user mode*

3: Normal reset

In ASE break mode*

RESETP assertion is

masked

H-UDI reset only

Normal operation

Notes: 1. Performs normal mode and ASE mode settings

ASEMD0 = H, normal mode

ASEMD0 = L, ASE mode

2. In ASE mode, reset hold is enabled by driving the

RESETP and TRST pins low for a

constant cycle. In this state, the CPU does not activate, even if

RESETP is driven high.

When

TRST is driven high, H-UDI operation is enabled, but the CPU does not activate.

The reset hold state is canceled by the following conditions:

• Another RESETP assertion (power-on reset)

• TRST reassertion

3. ASE mode is classified into two modes; ASE break mode to execute the firmware

program of an emulator and ASE user mode to execute the user program.

4. Make sure the

TRST pin is low when the power is turned on.

22.4.3

TDO Output Timing

The timing of data output from the TDO is switched by the command type set in the SDIR. The

timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ,

SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard.

When the H-UDI commands (H-UDI reset negate, H-UDI reset assert, and H-UDI interrupt) are

set, TDO is output at the TCK rising edge earlier than the JTAG standard by a half cycle.

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