SH7713 datasheet(787/904 Pages) RENESAS

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Section 23 List of Registers

Rev.1.50 Aug. 30, 2006 Page 747 of 860

REJ09B0288-0150

Section 23 List of Registers

The address map gives information on the on-chip I/O registers and is configured as described

below.

• Descriptions by functional module, in order of the corresponding section numbers.

• Access to reserved addresses which are not described in this list is prohibited.

• When registers consist of 16 or 32 bits, the addresses of the MSBs are given, on the

presumption of a big-endian system.

• Bit configurations of the registers are described in the same order as the Register Addresses

(by functional module, in order of the corresponding section numbers).

• Reserved bits are indicated by  in the bit name.

• No entry in the bit-name column indicates that the whole register is allocated as a counter or

for holding data.

• When registers consist of 16 or 32 bits, bits are described from the MSB side.

The order in which bytes are described is on the presumption of a big-endian system.

• Register states are described in the same order as the Register Addresses (by functional

module, in order of the corresponding section numbers).

• For the initial state of each bit, refer to the description of the register in the corresponding

section.

• The register states described are for the basic operating modes. If there is a specific reset for an

on-chip module, refer to the section on that on-chip module.

SH7713 Datasheet(PDF) 787 Page - Renesas Technology Corp