SH7721 datasheet(358/1524 Pages) RENESAS

358 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 296 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

IWRRD2

IWRRD1

IWRRD0

R/W

Idle Cycles for Read-Read in Another Space

Specify the number of idle cycles to be inserted after the

access to a memory that is connected to the space. The

target cycle is a read-read cycle of which continuous

accesses switch between different spaces.

000: No idle cycle inserted

001: 1 idle cycles inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

100: 6 idle cycles inserted

101: 8 idle cycles inserted

110: 10 idle cycles inserted

111: 12 idle cycles inserted

IWRRS2

IWRRS1

IWRRS0

R/W

Idle Cycles for Read-Read in Same Space

Specify the number of idle cycles to be inserted after the

access to a memory that is connected to the space. The

target cycle is a read-read cycle of which continuous

accesses are for the same space.

000: No idle cycle inserted

001: 1 idle cycles inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

100: 6 idle cycles inserted

101: 8 idle cycles inserted

110: 10 idle cycles inserted

111: 12 idle cycles inserted

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