SH7721 datasheet(354/1524 Pages) RENESAS

354 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 292 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W Description

DPRTY1

DPRTY0

R/W

DMA Burst Transfer Priority

Specify the priority for a refresh request/bus mastership request

during DMA burst transfer.

00: Accepts a refresh request and bus mastership request

during DMA burst transfer

01: Accepts a refresh request but does not accept a bus

mastership request during DMA burst transfer

10: Accepts neither a refresh request nor a bus mastership

request during DMA burst transfer

11: Reserved (Setting prohibited)

DMAIW2

DMAIW1

DMAIW0

R/W

Wait States between Access Cycles when DMA Single Address

is Transferred

Specify the number of idle cycles to be inserted after an access

to an external device with DACK when DMA single address

transfer is performed. The method of inserting idle cycles

depends on the contents of DMAIWA.

000: No idle cycle inserted

001: 1 idle cycle inserted

010: 2 idle cycles inserted

011: 4 idle cycled inserted

100: 6 idle cycled inserted

101: 8 idle cycle inserted

110: 10 idle cycles inserted

111: 12 idle cycled inserted

DMAIWA

R/W Method of Inserting Wait States between Access Cycles when

DMA Single Address is Transferred

Specifies the method of inserting the idle cycles specified by the

DMAIW1 and DMAIW0 bits. Clearing this bit will make this LSI

insert the idle cycles when another device, which includes this

LSI, drives the data bus after an external device with DACK

drove it. Setting this bit will make this LSI insert the idle cycles

even when the continuous accesses to an external device with

DACK are performed.

0: Inserts the idle cycles when another device drives the data

bus after an external device with DACK drove it.

1: Inserts the idle cycles every time when an external device

with DACK is accessed.

SH7721 Datasheet(PDF) 354 Page - Renesas Technology Corp

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