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SH7721 Datasheet(PDF) 351 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 351 Page - Renesas Technology Corp

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Section 9
Bus State Controller (BSC)
Rev. 3.00 Jan. 18, 2008 Page 289 of 1458
REJ09B0033-0300
9.3.4
Area 0 Memory Type and Memory Bus Width
The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to
select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. The memory bus
width of the other area is set by the register. The correspondence between the memory type,
external pins (MD3, MD4), and bus width is listed in the table below.
Table 9.4
Correspondence between External Pins (MD3 and MD4), Memory Type of CS0,
and Memory Bus Width
MD4
MD3
Memory Type
Bus Width
0
Reserved (Setting prohibited)
0
1
8 bits*
0
16 bits
1
1
Normal memory
32 bits
Note:
*
The bus width must not be specified as eight bits if the burst ROM (clock synchronous)
interface is selected.
9.3.5
Data Alignment
This LSI supports the big endian and little endian methods of data alignment. The data alignment
is specified using the external pin (MD5) at power-on reset as shown in table 9.5.
Table 9.5
Correspondence between External Pin (MD5) and Endians
MD5
Endian
0
Big endian
1
Little endian



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