SH7721 datasheet(353/1524 Pages) RENESAS

353 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 291 of 1458

REJ09B0033-0300

9.4.1

Common Control Register (CMNCR)

CMNCR is a 32-bit register that controls the common items for each area. Do not access external

memory other than area 0 until the CMNCR initialization is complete.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 15



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

BSD

R/W

Bus Access Start Timing Specification After Bus

Acknowledge

Specifies the bus access start timing after the external bus

acknowledge signal is received.

0: Starts the external access at the same timing as the

address drive start after the bus acknowledge signal is

received.

1: Starts the external access one cycle following the address

drive start after the bus acknowledge signal is received.



Reserved

This bit is always read as 0. The write value should always be

MAP

R/W

Space Specification

Selects the address map for the external address space. The

address maps to be selected are shown in tables 9.2 and 9.3.

0: Selects address map 1

1: Selects address map 2

BLOCK

R/W

Bus Lock Bit

Specifies whether or not the

BREQ signal is received.

0: Receives

BREQ

1: Does not receive

BREQ

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