SH7721 datasheet(352/1524 Pages) RENESAS

352 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 290 of 1458

REJ09B0033-0300

9.4

The BSC has the following registers. Refer to section 37, List of Registers, for more details on the

addresses and access size of these registers.

Do not access spaces other than CS0 until the termination of the setting the memory interface.

• Common control register (CMNCR)

• Bus control register for CS0 (CS0BCR)

• Bus control register for CS2 (CS2BCR)

• Bus control register for CS3 (CS3BCR)

• Bus control register for CS4 (CS4BCR)

• Bus control register for CS5A (CS5ABCR)

• Bus control register for CS5B (CS5BBCR)

• Bus control register for CS6A (CS6ABCR)

• Bus control register for CS6B (CS6BBCR)

• Wait control register for CS0 (CS0WCR)

• Wait control register for CS2 (CS2WCR)

• Wait control register for CS3 (CS3WCR)

• Wait control register for CS4 (CS4WCR)

• Wait control register for CS5A (CS5AWCR)

• Wait control register for CS5B (CS5BWCR)

• Wait control register for CS6A (CS6AWCR)

• Wait control register for CS6B (CS6BWCR)

• SDRAM control register (SDCR)

• Refresh timer control/status register (RTCSR)

• Refresh timer counter (RTCNT)

• Refresh time constant register (RTCOR)

• SDRAM mode register (SDMR2)

• SDRAM mode register (SDMR3)

SH7721 Datasheet(PDF) 352 Page - Renesas Technology Corp