SH7721 datasheet(355/1524 Pages) RENESAS

355 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 293 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 1. The write value should always

be 1.

ENDIAN

0/1*

Endian Flag

Samples the external pin for specifying endian on power-on

reset (MD5). All address spaces are defined by this bit. This

is a read-only bit.

0: The external pin for specifying endian (MD5) was low level

on power-on reset. This LSI is being operated as big

endian.

1: The external pin for specifying endian (MD5) was high

level on power-on reset. This LSI is being operated as

little endian.



Reserved

This bit is always read as 0. The write value should always

be 0.

HIZMEM

R/W

High-Z Memory Control

Specifies the pin state in standby mode for A25 to A0,

BS,

CSn, RD/WR, WEn(BEn)/DQMxx, and RD. When a bus is

released, these pins enter the high-impedance state

regardless of the setting of this bit.

0: High impedance in standby mode

1: Driven in standby mode

HIZCNT

R/W

High-Z Control

Specifies the state in standby mode and bus released for

CKIO, CKE,

RAS, and CAS.

0: High impedance in standby mode and bus released for

CKIO, CKE,

RAS, and CAS.

1: Driven in standby mode and bus released for CKIO, CKE,

RAS, and CAS.

Note:

The external pin (MD5) for specifying endian is sampled on power-on reset. When big

endian is specified, this bit is read as 0 and when little endian is specified, this bit is

read as 1.

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