SH7721 datasheet(523/1524 Pages) RENESAS

523 / 1524 page

Section 11

Clock Pulse Generator (CPG)

Rev. 3.00 Jan. 18, 2008 Page 461 of 1458

REJ09B0033-0300

11.4

The CPG has the following registers. Refer to section 37, List of Registers, for more details on the

addresses and access size of these registers.

• Frequency control register (FRQCR)

• USBH/USBF clock control register (UCLKCR)

11.4.1

Frequency Control Register (FRQCR)

The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify

whether a clock is output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1,

and the frequency division ratio of the internal clock and the peripheral clock.

Only word access can be used on the FRQCR register. FRQCR is initialized by a power-on reset,

but not initialized by a power-on reset at the WDT overflow. FRQCR retains its value in a manual

reset and in standby mode.

The write values to bits 14, 13, 11, 10, 7, 6, and 3 should always be 0.

Bit

Bit Name

Initial

Value

R/W

Description

PLL2EN

R/W

PLL2 Enable

PLL2EN specifies whether make the PLL circuit 2 ON in

clock operating mode 7.

PLL circuit 2 is ON in clock operating modes other than

mode 7 regardless of the PLL2EN setting.

0: PLL circuit 2 is OFF

1: PLL circuit 2 is ON

14, 13



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SH7721 Datasheet(PDF) 523 Page - Renesas Technology Corp