SH7721 datasheet(527/1524 Pages) RENESAS

527 / 1524 page

Section 11

Clock Pulse Generator (CPG)

Rev. 3.00 Jan. 18, 2008 Page 465 of 1458

REJ09B0033-0300

11.5

Changing Frequency

The frequency of the internal clock and peripheral clock can be changed either by changing the

multiplication rate of PLL circuit 1 or by changing the division rates of divider 1. All of these are

controlled by software through FRQCR. The methods are described below.

11.5.1

Changing Multiplication Rate

A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The on-

chip WDT counts the settling time.

1. In the initial state, the multiplication rate of PLL circuit 1 is 1.

2. Set a value that will become the specified oscillation settling time in the WDT and stop the

WDT. The following must be set:

TME bit in WTCSR

= 0: WDT stops

CKS2 to CKS0 bits in WTCSR: Division ratio of WDT count clock

WTCNT: Initial counter value

3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the IFC1

and IFC0 bits and PFC2 to PFC0 bits.

4. The processor pauses internally and the WDT starts incrementing. The internal and peripheral

clocks both stop and the WDT is supplied with the clock. The clock will continue to be output

at the CKIO pin.

5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins

operating again. The WDT stops after it overflows.

11.5.2

Changing Division Ratio

The WDT will not count unless the multiplication rate is changed simultaneously.

1. In the initial state, IFC1 and IFC0

= 00 and PFC2 to PFC0 = 011.

2. Set the IFC1, IFC0, and PFC2 to PFC0 bits to the new division ratio. The values that can be set

are limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the

wrong value is set, the processor will malfunction.

3. The clock is immediately supplied at the new division ratio.

SH7721 Datasheet(PDF) 527 Page - Renesas Technology Corp