SH7721 datasheet(529/1524 Pages) RENESAS

529 / 1524 page

Section 11

Clock Pulse Generator (CPG)

Rev. 3.00 Jan. 18, 2008 Page 467 of 1458

REJ09B0033-0300

Note: The values for CL1, CL2, and the damping resistance should be determined after

consultation with the crystal manufacturer.

XTAL

EXTAL

This LSI

CL2

CL1

Avoid crossing

signal lines

Figure 11.2

Points for Attention when Using Crystal Resonator

(2)

Bypass Capacitors

Insert a laminated ceramic capacitor as a bypass capacitor for each V

SS/VCC pair. Mount the bypass

capacitors to the power supply pins, and use components with a frequency characteristic suitable

for the operating frequency of the LSI, as well as a suitable capacitance value.

(3)

When Using a PLL Oscillator Circuit

Keep the wiring from the PLL V

CC and VSS connection pattern to the power supply pins short, and

make the pattern width large, to minimize the inductance component.

Connect the EXTAL pin to V

CC or VSSQ and make the XTAL pin open in clock mode 7.

The analog power supply system of the PLL is sensitive to a noise. Therefore the system

malfunction may occur by the intervention with other power supply. Do not supply the analog

power supply with the same resource as the digital power supply of V

CC and VCCQ.

SH7721 Datasheet(PDF) 529 Page - Renesas Technology Corp