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SH7721 Datasheet(PDF) 525 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 525 Page - Renesas Technology Corp |
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525 / 1524 page ![]() Section 11 Clock Pulse Generator (CPG) Rev. 3.00 Jan. 18, 2008 Page 463 of 1458 REJ09B0033-0300 Bit Bit Name Initial Value R/W Description 2 1 0 PFC2 PFC1 PFC0 0 1 1 R/W R/W R/W Peripheral Clock Frequency Division Ratio These bits specify the division ratio of the peripheral clock (P φ) frequency with respect to the output frequency of PLL circuit 1. 000: × 1 time 001: × 1/2 time 010: × 1/3 time 011: × 1/4 time 100: × 1/6 time Other than above: Reserved (setting prohibited) |
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