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SH7721 Datasheet(PDF) 694 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 694 Page - Renesas Technology Corp |
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694 / 1524 page  Section 18 Serial Communication Interface with FIFO (SCIF) Rev. 3.00 Jan. 18, 2008 Page 632 of 1458 REJ09B0033-0300 No Yes No Wait Yes 1. Set the receive trigger number in SCFCR. 2. Reset the receive FIFO. 3. Wait for one bit interval. 4. Reception is started when the RE bit in SCSCR is set to 1. 5. Read receive data while the RDF bit is 1. 6. After the end of reception, clear the RE bit to 0. Start of reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR Set RFRST bit in SCFCR to 1 Clear RFRST bit in SCFCR to 0 1-bit interval elapsed? Set RE bit in SCSCR When using receive FIFO data interrupt, set RIE bit to 1 RDF =1? Read receive trigger number of receive data bytes from SCFRDR Clear RE bit in SCSCR to 0 End of reception 1 2 3 4 5 6 Figure 18.15 Sample Serial Reception Flowchart (2) (Second and Subsequent Reception) |
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