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SH7721 Datasheet(PDF) 695 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 695 Page - Renesas Technology Corp

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Section 18
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 633 of 1458
REJ09B0033-0300
(6)
Data Transfer Operations (Simultaneous Serial Data Transmission and Reception)
Figure 18.16 shows sample flowcharts for simultaneous serial transmission and reception.
No
Yes
No
Yes
1. Set the receive trigger number
in SCFCR.
2. Write the remaining transmit data
to SCFTDR, and if there is receive
data in the FIFO, read receive data
until there is less than the receive
trigger setting number, read the
TDFE and RDF bits in SCSSR, and
if 1, clear to 0.
3. Transmission/reception is started
when the TE and RE bits in SCSCR
are set to 1. The TE and RE bits
must be set simultaneously.
4. After the end of transmission/reception,
clear the TE and RE bits to 0.
Start of simultaneous
transmission/reception
Set receive trigger number in RTRG1
and RTRG0 in SCFCR
Write remaining transmit data to SCFTDR
Read TDFE and RDF bits in SCSSR
TDFE =1?
RDF =1?
Write 0 to TDFE and RDF bits in
SCSSR after reading 1 from them
Set TE and RE bits in SCSCR
simultaneously
When using transmit FIFO data interrupt,
set TIE bit to 1
When using receive FIFO data interrupt,
set RIE bit to 1
TDFE =1?
RDF =1?
Read receive trigger number of receive
data bytes from SCFRDR
Clear TE and RE bits in SCSCR to 0
End of
transmission/reception
2
1
3
4
Figure 18.16
Sample Simultaneous Serial Transmission and Reception Flowchart (1)
(First Transfer after Initialization)



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