SH7721 datasheet(697/1524 Pages) RENESAS

697 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 635 of 1458

REJ09B0033-0300

18.5

Interrupt Sources and DMAC

In asynchronous mode, the SCIF supports six interrupts: transmit-FIFO-data-empty, transmit data

stop, receive-error, receive-FIFO-data-full, break receive, and receive data ready. A common

interrupt vector is assigned to each interrupt source.

In synchronous mode, the SCIF supports two interrupts: transmit-FIFO-data-empty and receive-

FIFO-data-full.

Table 18.4 shows the interrupt sources. The interrupt sources are enabled or disabled by means of

the TIE, RIE, ERIE, BRIE, DRIE, and TSIE bits in SCSCR.

When the TDFE flag in SCSSR is set to 1, the transmit-FIFO-data-empty interrupt request is

generated. When the TSF flag in SCSSR is set to 1, the transmit-data-stop interrupt request is

generated. Activating the DMAC and transferring data can be performed by the transmit-FIFO-

data-empty interrupt and data stop interrupt requests. The DMAC transfer request is automatically

cleared when the number of data written to SCFTDR by the DMAC is increased more than that of

setting transmit triggers.

When the RDF flag in SCSSR is set to 1, a receive-FIFO-data-full interrupt request is generated.

Activating the DMAC and transferring data can be performed by the receive-FIFO-data-full

interrupt request. The DMAC transfer request is automatically cleared when receive data is read

from SCFRDR by the DMAC until the number of receive data in SCFRDR is decreased less than

that of receive triggers.

When executing the data transmission and reception, set the DMAC, and then set SCIF after

entered in the enabled state. The completion of the DMA transfer is the completion of

transmission and reception. For the DMAC setting procedure, see section 10, Direct Memory

Access Controller (DMAC).

An interrupt request is generated when the ER flag in SCSSR is set to1; the BRK flag in SCSSR is

set to 1; the DR flag in SCSSR is set to 1; or the TSF flag in SCSSR is set to 1. A common

interrupt vector is assigned to each interrupt source. The activation of DMAC and generation of an

interrupt are not executed at the same time by the same source. When activating the DMAC, carry

out the following procedure.

• Set the interrupt enable bits (TIE, RIE) that correspond to the interrupt sources used for

activation of the DMAC. Clear the other interrupt enable bits (TSIE, ERIE, BRIE, and DRIE)

to 0.

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