SH7721 datasheet(700/1524 Pages) RENESAS

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Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 638 of 1458

REJ09B0033-0300

(4)

Receive Data Sampling Timing and Receive Margin

An example with a sampling rate 1/16 is given. The SCIF operates on a base clock with a

frequency of 8 times the transfer rate. In reception, the SCIF synchronizes internally with the fall

of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the

eighth base clock pulse. The timing is shown in figure 18.17.

0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5

Base clock

Receive

data (RxD)

Synchro-

nization

sampling

timing

Data

sampling

timing

8 clocks

16 clocks

Start bit

−7.5 clocks

+7.5 clocks

Figure 18.17

Receive Data Sampling Timing in Asynchronous Mode

The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).

Equation 1:

M = 0.5 − 1

D − 0.5

− (L − 0.5) F −

(1 + F) × 100% ....................... (1)

M: Receive margin (%)

N: Ratio of clock frequency to bit rate (N = 16)

D: Clock duty cycle (D = 0 to 1.0)

L: Frame length (L = 9 to 12)

F: Absolute deviation of clock frequency

From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).

When D = 0.5 and F = 0:

= (0.5 – 1/(2 × 16)) × 100%

= 46.875% ...................................................................................................... (2)

This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.

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