SH7721 datasheet(696/1524 Pages) RENESAS

696 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 634 of 1458

REJ09B0033-0300

Yes

Wait

1. Set the receive trigger number and

transmit trigger number in SCFCR.

2. Reset the receive FIFO and transmit

FIFO.

3. Write transmit data to SCFTDR, and

if there is receive data in the FIFO,

read receive data until there is less

than the receive trigger setting number,

read the TDFE and RDF bits in SCSSR,

and if 1, clear to 0.

4. Wait for one bit interval.

5. Transmission/reception is started when

the TE and RE bits in SCSCR are set

to 1. The TE and RE bits must be set

simultaneously.

6. After the end of transmission/reception,

clear the TE and RE bits to 0.

Start of simultaneous

transmission/reception

Set receive trigger number in RTRG1

and RTRG0 in SCFCR, and set transmit

trigger number in TTRG1 and TTRG0

Set TFRST and RFRST bits in

SCFCR to 1

Clear TFRST and RFRST bits in

SCFCR to 0

Write transmit data to SCFTDR

Read TDFE and RDF bits in SCSSR

TDFE =1?

RDF =1?

Write 0 to TDFE and RDF bits in

SCSSR after reading 1 from them

1-bit interval elapsed?

Set TE and RE bits in SCSCR

simultaneously

When using transmit FIFO data

interrupt, set TIE bit to 1

When using receive FIFO data

interrupt, set RIE bit to 1

TDFE =1?

RDF =1?

Read receive trigger number of

receive data bytes from SCFRDR

End of

transmission/reception

Clear TE and RE bits in SCSCR to 0

Figure 18.16

Sample Simultaneous Serial Transmission and Reception Flowchart (2)

(Second and Subsequent Transfer)

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