SH7721 datasheet(729/1524 Pages) RENESAS

729 / 1524 page

Section 20

2C Bus Interface (IIC)

Rev. 3.00 Jan. 18, 2008 Page 667 of 1458

REJ09B0033-0300

TDRE

Data n

TEND

ICDRS

ICDRR

TRS

ICDRT

SCL

(Master output)

SDA

(Master output)

SDA

(Slave output)

SCL

(Slave output)

Bit 7

Slave transmit mode

Slave receive

mode

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

[3] Clear TEND

[5] Clear TDRE

[4] Read ICDRR (dummy read)

after clearing TRS

User

processing

Figure 20.10

Slave Transmit Mode Operation Timing (2)

20.4.5

Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and transmit data, and the

slave device returns an acknowledge signal. For slave receive mode operation timing, refer to

figures 20.11 and 20.12. The reception procedure and operations in slave receive mode are

described below.

1. Set the ICE bit in ICCR1 to 1. Set the MLS bit in ICMR and the CKS4 to CKS0 bits in

ICCKS1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive

mode, and wait until the slave address matches.

2. When the slave address matches in the first frame following detection of the start condition,

the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th

clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the

read data show the slave address and R/

W, it is not used.)

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