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SH7721 Datasheet(PDF) 726 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 726 Page - Renesas Technology Corp

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Section 20
I
2C Bus Interface (IIC)
Rev. 3.00 Jan. 18, 2008 Page 664 of 1458
REJ09B0033-0300
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. The operation returns to the slave receive mode.
TDRE
TEND
ICDRS
ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
[3] Read ICDRR
1
A
21
34
56
78
9
9
A
TRS
RDRF
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
Bit 7
Master transmit mode
Master receive mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User
processing
Data 1
Data 1
Figure 20.7
Master Receive Mode Operation Timing (1)



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