SH7721 datasheet(722/1524 Pages) RENESAS

722 / 1524 page

Section 20

2C Bus Interface (IIC)

Rev. 3.00 Jan. 18, 2008 Page 660 of 1458

REJ09B0033-0300

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Transfer Rate

CKS4 CKS3 CKS2 CKS1 CKS0

Peripheral

Clock

φ = 10

MHz

φ = 16

MHz

φ = 20

MHz

φ = 25

MHz

φ = 30

MHz

φ = 32

MHz

φ/800

13kHz

20kHz

25kHz

31kHz

38kHz

40kHz

φ/896

11kHz

18kHz

22kHz

28kHz

33kHz

36kHz

φ/1024

10kHz

16kHz

20kHz

24kHz

29kHz

31kHz

Note:

In master mode, a transfer rate of 300 kHz or lower should be used.

In slave mode, a transfer rate of 400 kHz or lower should be used.

20.4

Operation

20.4.1

2C Bus Format

Figure 20.3 shows the I

2C bus formats. Figure 20.4 shows the I2C bus timing. The first frame

following a start condition always consists of 8 bits.

SLA

DATA

(a) I2C bus format (FS = 0)

(b) I2C bus format (Start condition retransmission, FS = 0)

n: Transfer bit count

(n = 1 to 8)

m: Transfer frame count

≥ 1)

SLA

DATA

SLA

DATA

n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)

m1 and m2: Transfer frame count (m1 and m2

≥ 1)

Figure 20.3

2C Bus Formats

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