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SH7721 Datasheet(PDF) 718 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 718 Page - Renesas Technology Corp

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Section 20
I
2C Bus Interface (IIC)
Rev. 3.00 Jan. 18, 2008 Page 656 of 1458
REJ09B0033-0300
Bit
Bit Name
Initial
Value
R/W
Description
4
NACKF
0
R/W
No Acknowledge Detection Flag
[Setting condition]
• When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER is
1
[Clearing condition]
• When 0 is written in NACKF after reading NACKF = 1
3
STOP
0
R/W
Stop Condition Detection Flag
[Setting conditions]
• In master mode: when a stop condition is detected
after frame transfer is completed
• In slave mode: when a stop condition is detected after
the address set in SAR matches the salve address
that comes as the first byte after the detection of a
start condition
[Clearing condition]
• When 0 is written in STOP after reading STOP = 1
2
AL/OVE
0
R/W
Arbitration Lost Flag/Overrun Error Flag
This flag indicates that arbitration was lost in master
mode with the I
2C bus format.
When two or more master devices attempt to seize the
bus at nearly the same time, if the I
2C bus interface
detects data differing from the data it sent, it sets AL to 1
to indicate that the bus has been taken by another
master.
[Setting conditions]
• If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
• When the SDA pin outputs high in master mode while
a start condition is detected
[Clearing condition]
• When 0 is written in AL/OVE after reading AL/OVE =
1



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