SH7721 datasheet(715/1524 Pages) RENESAS

715 / 1524 page

Section 20

2C Bus Interface (IIC)

Rev. 3.00 Jan. 18, 2008 Page 653 of 1458

REJ09B0033-0300

20.3.4

2C Bus Interrupt Enable Register (ICIER)

ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be

transferred, and confirms acknowledge bits to be received.

Bit

Bit Name

Initial

Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When the TDRE bit in ICSR is set to 1, this bit enables or

disables the transmit data empty interrupt (TXI).

0: Transmit data empty interrupt request (TXI) is disabled.

1: Transmit data empty interrupt request (TXI) is enabled.

TEIE

R/W

Transmit End Interrupt Enable

This bit enables or disables the transmit end interrupt

(TEI) at the rising of the ninth clock while the TDRE bit in

ICSR is 1. TEI can be canceled by clearing the TEND bit

or the TEIE bit to 0.

0: Transmit end interrupt request (TEI) is disabled.

1: Transmit end interrupt request (TEI) is enabled.

RIE

R/W

Receive Interrupt Enable

This bit enables or disables the receive data full interrupt

request (RXI) when a receive data is transferred from

ICDRS to ICDRR and the RDRF bit in ICSR is set to 1.

RXI can be canceled by clearing the RDRF or RIE bit to

0: Receive data full interrupt request (RXI) is disabled.

1: Receive data full interrupt request (RXI) is enabled.

NAKIE

R/W

NACK Receive Interrupt Enable

This bit enables or disables the NACK receive interrupt

request (NAKI) when the NACKF and AL bits in ICSR are

set to 1. NAKI can be canceled by clearing the NACKF,

OVE, or NAKIE bit to 0.

0: NACK receive interrupt request (NAKI) is disabled.

1: NACK receive interrupt request (NAKI) is enabled.

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