SH7721 datasheet(711/1524 Pages) RENESAS

711 / 1524 page

Section 20

2C Bus Interface (IIC)

Rev. 3.00 Jan. 18, 2008 Page 649 of 1458

REJ09B0033-0300

20.3.1

2C Bus Control Register 1 (ICCR1)

ICCR1 enables or disables the I

2C bus interface, controls transmission or reception, and selects

master or slave mode, transmission or reception, and transfer clock frequency in master mode.

Bit

Bit Name

Initial

Value

R/W

Description

ICE

R/W

2C Bus Interface Enable

0: This module is halted.

1: This bit is enabled for transfer operations.

RCVD

R/W

Reception Disable

This bit enables or disables the next operation when TRS

is 0 and ICDRR is read.

0: Enables next reception

1: Disables next reception

MST

TRS

R/W

Master/Slave Select

Transmit/Receive Select

In master mode with the I

2C bus format, when arbitration

is lost, MST and TRS are both reset by hardware,

causing a transition to slave receive mode. Modification

of the TRS bit should be made between transfer frames.

After data receive has been started in slave receive

mode, when the first seven bits of the receive data agree

with the slave address that is set to SAR and the eighth

bit is 1, TRS is automatically set to 1.

Operating modes are described below according to MST

and TRS combination.

00: Slave receive mode

01: Slave transmit mode

10: Master receive mode

11: Master transmit mode

3 to 0



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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