SH7721 datasheet(707/1524 Pages) RENESAS

707 / 1524 page

Section 20

2C Bus Interface (IIC)

IFIIC10A_000020020200

Rev. 3.00 Jan. 18, 2008 Page 645 of 1458

REJ09B0033-0300

Section 20

2C Bus Interface (IIC)

The I

2C bus interface supports and provides a subset of the Philips I2C bus (inter-IC bus) interface

functions. The register configuration that controls the I

2C bus differs partly from the Philips

configuration, however.

Figure 20.1 shows a block diagram of the I

2C bus interface.

Figure 20.2 shows an example of I/O pin connections to external circuits.

20.1

Features

• Continuous transmission/reception

Since the shift register, transmit data register, and receive data register are independent from

each other, the continuous transmission/reception can be performed.

• Start and stop conditions generated automatically in master mode

• Selection of acknowledge output levels when receiving

• Automatic loading of acknowledge bit when transmitting

• Bit synchronization/wait function

In master mode, the state of SCL is monitored per bit, and the timing is synchronized

automatically.

If transmission/reception is not yet possible, set the SCL to low until preparations are

completed.

• Six interrupt sources

Transmit data empty (including slave-address match), transmit end, receive data full (including

slave-address match), arbitration lost, NACK detection, and stop condition detection

• Direct bus drive

Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive

function is selected.

SH7721 Datasheet(PDF) 707 Page - Renesas Technology Corp