SH7721 datasheet(720/1524 Pages) RENESAS

720 / 1524 page

Section 20

2C Bus Interface (IIC)

Rev. 3.00 Jan. 18, 2008 Page 658 of 1458

REJ09B0033-0300

20.3.7

2C Bus Transmit Data Register (ICDRT)

ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the

space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to

ICDRS and starts transferring data. If the next transfer data is written to ICDRT during

transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and

when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of

ICDRT is H'FF.

20.3.8

2C Bus Receive Data Register (ICDRR)

ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR

transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a

receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is

H'FF.

20.3.9

2C Bus Shift Register (ICDRS)

ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from

ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from

ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the

CPU.

20.3.10

2C Bus Master Transfer Clock Select Register (ICCKS)

ICCKS is enabled in master mode and selects a transfer clock used in master mode. Specify

ICCKS according to the required transfer rate. For transfer rate, see table 20.2.

Bit

Bit Name

Initial

Value

R/W

Description

7 to 5



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

CKS4

CKS3

CKS2

CKS1

CKS0

R/W

Master Transfer Clock Select 4 to 0

Specify these bits according to the required

transfer rate in master mode. In slave mode, these

bits are used to ensure the data setup time in

transmit mode.

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