SH7721 datasheet(724/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 20

2C Bus Interface (IIC)

Rev. 3.00 Jan. 18, 2008 Page 662 of 1458

REJ09B0033-0300

5. The transmit data after the second byte is written to ICDRT every time TDRE is set.

6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last

byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the

receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or

NACKF.

7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.

TDRE

SCL

(Master output)

SDA

(Master output)

SDA

(Slave output)

TEND

[5] Write data to ICDRT (third byte)

ICDRT

ICDRS

[2] Instruction of start

condition issuance

[3] Write data to ICDRT (first byte)

[4] Write data to ICDRT (second byte)

User

processing

Bit 7

Slave address

Address + R/

Data 1

Data 2

Address + R/

Bit 6

Bit 7

Bit 6

Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Figure 20.5

Master Transmit Mode Operation Timing (1)

SH7721 Datasheet(PDF) 724 Page - Renesas Technology Corp