SH7721 datasheet(725/1524 Pages) RENESAS

725 / 1524 page

Section 20

2C Bus Interface (IIC)

Rev. 3.00 Jan. 18, 2008 Page 663 of 1458

REJ09B0033-0300

TDRE

[6] Issue stop condition. Clear TEND.

[7] Set slave receive mode

TEND

ICDRT

ICDRS

SCL

(Master output)

SDA

(Master output)

SDA

(Slave output)

Bit 7

Bit 6

Data n

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

[5] Write data to ICDRT

User

processing

Figure 20.6

Master Transmit Mode Operation Timing (2)

20.4.3

Master Receive Operation

In master receive mode, the master device outputs the receive clock, receives data from the slave

device, and returns an acknowledge signal. For master receive mode operation timing, refer to

figures 20.7 and 20.8. The reception procedure and operations in master receive mode are shown

below.

1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master

transmit mode to master receive mode. Then, clear the TDRE bit to 0.

2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,

and data received, in synchronization with the internal clock. The master device outputs the

level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.

3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise

of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF

is cleared to 0.

4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th

receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is

fixed low until ICDRR is read.

5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.

This enables the issuance of the stop condition after the next reception.

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