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SH7721 Datasheet(PDF) 730 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 730 Page - Renesas Technology Corp

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Section 20
I
2C Bus Interface (IIC)
Rev. 3.00 Jan. 18, 2008 Page 668 of 1458
REJ09B0033-0300
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
ICDRS
ICDRR
12
1
34
56
78
9
9
A
A
RDRF
Data 1
Data 2
Data 1
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
Bit 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
[2] Read ICDRR (dummy read)
[2] Read ICDRR
User
processing
Figure 20.11
Slave Receive Mode Operation Timing (1)



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