SH7721 datasheet(734/1524 Pages) RENESAS

734 / 1524 page

Section 20

2C Bus Interface (IIC)

Rev. 3.00 Jan. 18, 2008 Page 672 of 1458

REJ09B0033-0300

Yes

RDRF=1 ?

Yes

RDRF=1 ?

Last receive

- 1?

Mater receive mode

Clear TEND in ICSR

Clear TRS in ICCR1 to 0

Clear TDRE in ICSR

Clear ACKBT in ICIER to 0

Dummy-read ICDRR

Read RDRF in ICSR

Read ICDRR

Set ACKBT in ICIER to 1

Set RCVD in ICCR1 to 1

Read ICDRR

Read RDRF in ICSR

Write 0 to BBSY

and SCP

Read STOP in ICSR

Read ICDRR

Clear RCVD in ICCR1 to 0

Clear MST in ICCR1 to 0

Note: 1. Do not activate an interrupt during the execution of steps [1] to [3].

End

Yes

STOP=1 ?

Yes

[1]

Clear TEND, select master receive mode, and then clear TDRE.*1*2

[2]

Set acknowledge to the transmit device.*1

[3]

Dummy-read ICDDR.*

[4]

Wait for 1 byte to be received

[5]

Check whether it is the (last receive - 1).

[6]

Read the receive data last.

[7]

Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).

[8]

Read the (final byte - 1) of receive data.

[9]

Wait for the last byte to be receive.

[10] Clear the STOP flag.

[11] Issue the stop condition.

[12] Wait for the creation of stop condition.

[13] Read the last byte of receive data.

[14] Clear RCVD.

[15] Set slave receive mode.

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[11]

[12]

[13]

Clear STOP in ICSR.

[10]

[14]

[15]

2. When one byte is received, steps [2] to [6] are skipped; step [7] is executed

after step [1]. Setp [8] is ICDRR dummy read.

Figure 20.15

Sample Flowchart for Master Receive Mode

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