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SH7721 Datasheet(PDF) 738 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 738 Page - Renesas Technology Corp |
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738 / 1524 page ![]() Section 20 I 2C Bus Interface (IIC) Rev. 3.00 Jan. 18, 2008 Page 676 of 1458 REJ09B0033-0300 20.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull- up resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 20.21 shows the timing of the bit synchronous circuit and table 20.4 shows the time when SCL output changes from low to Hi-Z then SCL is monitored. SCL VIH SCL monitor timing reference clock Internal SCL Figure 20.18 The Timing of the Bit Synchronous Circuit Table 20.4 Time for Monitoring SCL CKS3 CKS2 Time for Monitoring SCL 0 7.5 tpcyc 0 1 19.5 tpcyc 0 17.5 tpcyc 1 1 41.5 tpcyc |
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