SH7721 datasheet(739/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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739 / 1524 page

Section 20

2C Bus Interface (IIC)

Rev. 3.00 Jan. 18, 2008 Page 677 of 1458

REJ09B0033-0300

20.7

Usage Notes

A stop condition or retransmit start condition should be issued after the falling edge of the ninth

clock is recognized. The falling edge of the ninth clock is recognized by checking the SCLO bit in

the I

2C bus control register 2 (ICCR2).

A stop condition or retransmit start condition may not be output normally if issuance of a stop or

retransmit start condition is attempted with a certain timing under either of the following cases.

There is no problem in uses under conditions other than the blow.

1. When the rising speed of SCL is lowered due to the load of the SCL line (load capacitance or

pull-up resistance) exceeding the time defined in section 20.6, Bit Synchronous Circuit.

2. When the bit synchronous circuit works because the low-level period between the eighth and

ninth clock pulses is extended by the slave device.

SH7721 Datasheet(PDF) 739 Page - Renesas Technology Corp