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SH7721 Datasheet(PDF) 743 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 743 Page - Renesas Technology Corp |
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743 / 1524 page ![]() Section 21 Serial I/O with FIFO (SIOF) Rev. 3.00 Jan. 18, 2008 Page 681 of 1458 REJ09B0033-0300 21.2 Input/Output Pins The pin configuration in this module is shown in table 21.1. Table 21.1 Pin Configuration Channel Pin Name Abbreviation* I/O Function SIOF0_MCLK SIOFMCLK Input Master clock input SIOF0_SCK SIOFSCK I/O Serial clock (common to transmission/reception) SIOF0_SYNC SIOFSYNC I/O Frame synchronous signal (common to transmission/reception) SIOF0_TxD SIOFTxD Output Transmit data 0 SIOF0_RxD SIOFRxD Input Receive data SIOF1_MCLK SIOFMCLK Input Master clock input SIOF1_SCK SIOFSCK I/O Serial clock (common to transmission/reception) SIOF1_SYNC SIOFSYNC I/O Frame synchronous signal (common to transmission/reception) SIOF1_TxD SIOFTxD Output Transmit data 1 SIOF1_RxD SIOFRxD Input Receive data Note: * The pins for channel 0 and channel 1 are collectively called SIOFMCLK, SIOFSCK, SIOFSYNC, SIOFTxD, and SIOFRxD in the following descriptions. |
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