SH7721 datasheet(744/1524 Pages) RENESAS

744 / 1524 page

Section 21

Serial I/O with FIFO (SIOF)

Rev. 3.00 Jan. 18, 2008 Page 682 of 1458

REJ09B0033-0300

21.3

The SIOF has the following registers. Refer to section 37, List of Registers, for more details on the

addresses and states of these registers in each operating mode. In the register descriptions

following this section, channel numbers are omitted.

(1) Channel 0

• Mode register_0 (SIMDR_0)

• Control register_0 (SICTR_0)

• Transmit data register_0 (SITDR_0)

• Receive data register_0 (SIRDR_0)

• Transmit control data register_0 (SITCR_0)

• Receive control data register_0 (SIRCR_0)

• Status register_0 (SISTR_0)

• Interrupt enable register_0 (SIIER_0)

• FIFO control register_0 (SIFCTR_0)

• Clock select register_0 (SISCR_0)

• Transmit data assign register_0 (SITDAR_0)

• Receive data assign register_0 (SIRDAR_0)

• Control data assign register_0 (SICDAR_0)

(2) Channel 1

• Mode register_1 (SIMDR_1)

• Control register_1 (SICTR_1)

• Transmit data register_1 (SITDR_1)

• Receive data register_1 (SIRDR_1)

• Transmit control data register_1 (SITCR_1)

• Receive control data register_1 (SIRCR_1)

• Status register_1 (SISTR_1)

• Interrupt enable register_1 (SIIER_1)

• FIFO control register_1 (SIFCTR_1)

• Clock select register_1 (SISCR_1)

• Transmit data assign register_1 (SITDAR_1)

• Receive data assign register_1 (SIRDAR_1)

• Control data assign register_1 (SICDAR_1)

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